The present invention relates to integrated circuit packages and, more particularly, to wafer-level packages for integrated circuits. Integrated circuits (ICs) are manufactured as wafers, each wafer containing many individual circuits (die). After fabrication, a wafer is cut (“singulated”) into individual die. Each die is then encapsulated in a plastic or ceramic package or is attached to a ceramic cap.
Each die includes several electrical contact pads. During packaging, each of these contact pads is connected to a respective lead or another external structure. In one common practice, a bonding wire is welded between each contact pad and a respective lead. The leads or other structures are used to electrically connect a completed IC to a circuit board or the like, such as by soldering. These solder connections often also provide the sole mechanical connection between the IC and the circuit board.
IC wafer fabrication is commonly referred to as the “front-end” process of IC fabrication. An IC wafer can be fabricated relatively efficiently, because all die on the wafer are fabricated concurrently (i.e., in parallel), such as by a photolithographic process, in which an entire layer of the wafer is produced at one time using a lithographic mask. Thus, the amount of time required to fabricate a wafer is largely independent of the number of die on the wafer. However, after the die are singulated, packaging the individual die (the “back-end” process of IC fabrication) is time consuming and expensive, because each die must be packaged individually (i.e., serially). Given the reliance of the electronics industry on ICs and the large number of ICs installed every week, reducing the cost of each IC can lead to a substantial overall cost saving.